Original technical submissions on, but not limited to, the following topics are invited:
1) SYSTEM-LEVEL CAD 1.1 System Design - System-level specification, modeling, and simulation - System design flows and methods - HW/SW co-design, co-simulation, co-optimization, and co-exploration - HW/SW platforms for rapid prototyping - System design case studies and applications - System-level issues for 3D integration - Micro-architectural transformation - Memory architecture and system synthesis - System communication architecture - Network-on-chip design methodologies and CAD - Modeling and simulation of heterogeneous platforms - High-level synthesis for heterogeneous computing - Power/performance analysis of heterogeneous and cloud platforms - Programming environment of heterogeneous computing - Application driven heterogeneous platforms for big data, machine learning etc. - Applications and designs for systems based on optical devices 1.2 Embedded Systems and Cyberphysical Systems - Multi-core/multi-processors systems - HW/SW co-design for embedded systems - Static and dynamic reconfigurable architectures - Memory hierarchies and management - System-level consideration of custom memory/storage architectures - Application-specific instruction-set processors (ASIPs) - CAD for Internet-of-Things (IoT) and sensor networks - Design issues for Internet-of-Things (IoT) Devices - Modeling and analysis of CPS - CAD for automotive systems and power electronics - Dependable and safe CPS design - Analysis and optimization of data centers - CAD for display electronics - Green computing (smart grid, energy, solar panels, etc.) 1.3 Neural Network and Neuromorphic Computing - Hardware and devices for neuromorphic and neural network computing - Design method for learning on a chip - Systems for neural computing (including deep neural networks) - Neural network acceleration techniques including GPGPU, FPGA and dedicated ASICs - CAD for bio-inspired and neuromorphic systems 1.4 Embedded Systems Software and Software Security - Real-time software and operating systems - Middleware and virtual machines, runtime support and resource management - Timing analysis and WCET - Profiling and compilation techniques, domain-specific embedded libraries - Design exploration, synthesis, validation, verification, and optimization - Software techniques and programming models for multicores, GPUs, and multithreaded embedded architectures - System and embedded software security techniques - Malware and Cloud security - Security and privacy for the Internet of Things - Embedded software forensics 1.5 Hardware Security - Hardware-based security (CAD for PUF’s, RNG, AES etc) - Detection and prevention of hardware Trojans - Side-channel attacks, fault attacks and countermeasures - Split Manufacturing for security - Design and CAD for security - Security implications of CAD - Cyberphysical system security - Nanoelectronic security - Supply chain security and anti-counterfeiting 1.6 Low Power and Approximate Computing in System Design - Power and thermal estimation, analysis, optimization, and management techniques for hardware and software systems - Energy- and thermal aware application mapping and scheduling - Energy- and thermal-aware dark silicon system design and optimization - Energy- and thermal-aware architectures, algorithms and techniques - Run-time management for the dark silicon - New hardware techniques for approximate/stochastic computing
2) SYNTHESIS, VERIFICATION, & PHYSICAL DESIGN 2.1 High-Level, Behavioral, and Logic Synthesis and Optimization - High-level/Behavioral/Logic synthesis - Technology-independent optimization and technology mapping - Functional and logic timing ECO - Resource scheduling, allocation, and synthesis - Interaction between logic synthesis and physical design 2.2 Testing, Validation, Simulation, and Verification - High-level/Behavioral/Logic modeling and validation - High-level/Behavioral/Logic simulation - Formal, semi-formal, and assertion-based verification - Equivalence and property checking - Emulation and hardware simulation/acceleration - Post-silicon functional validation - Digital fault modeling and simulation - Delay, current-based, low-power test - ATPG, BIST, DFT, and compression - Memory test and repair - Core, board, system, and 3D IC test - Post-silicon validation and debug - Analog, mixed-signal, and RF test 2.3 Cell-Library Design, Partitioning, Floorplanning, Placement - Cell-library design and optimization - Transistor and gate sizing - High-level physical design and synthesis - Estimation and hierarchy management - 2D and 3D partitioning, floorplanning, and placement - Post-placement optimization - Buffer insertion and interconnect planning 2.4 Clock Network Synthesis, Routing, and Post-Layout Optimization and Verification - 2D and 3D clock network synthesis - 2D and 3D global and detailed routing - Package-/Board-level routing and chip-package-board co-design - Post-layout/-silicon optimization - Layout and routing issues for optical interconnects
3) SOC ANALYSIS, DESIGN, SIMULATION, & TESTING 3.1 Design for Manufacturability and Design for Reliability - Process technology characterization, extraction, and modeling - CAD for design/manufacturing interfaces - CAD for reticle enhancement and lithography-related design - Variability analysis and statistical design and optimization - Yield estimation and design for yield - Physical verification and design rule checking - DFM for emerging devices (3D, nanophotonics, non-volatile logic/memory, etc.) - Machine learning for smart manufacturing and process control - Analysis and optimization for device-level reliability issues (stress, aging effects, ESD, etc.) - Analysis optimization for interconnect reliability issues (electromigration, thermal, etc.) - Reliability issues related to soft errors - Design for resilience and robustness - Reliability issues for emerging devices (3D, optical, non-volatile, etc.) 3.2 Timing, Power and Signal Integrity Analysis and Optimization - Deterministic and statistical static timing analysis and optimization - Power and leakage analysis and optimization - Circuit and interconnect-level low power design issues - Power/ground network analysis and synthesis - Signal integrity analysis and optimization 3.3 CAD for Analog/Mixed-Signal/RF and Multi-Domain Modeling - CAD for analog, mixed-signal, RF - CAD for mixed-domain (semiconductor, nanoelectronic, MEMS, and electrooptical) devices, circuits, and systems - CAD for nanophotonics and optical devices - Analog, mixed-signal, and RF noise modeling and simulation - Device, interconnect and circuit extraction and simulation - Package modeling and analysis - EM simulation and optimization - Behavior modeling of devices and interconnect - Modeling of complex dynamical systems (molecular dynamics, fluid dynamics, computational finance, etc.)
4) CAD FOR EMERGING TECHNOLOGIES, PARADIGMS, & APPLICATIONS 4.1 Biological Systems and Electronics, Brain Inspired Computing, and New Computing Paradigms - CAD for biological computing systems - CAD for systems and synthetic biology - CAD for bio-electronic devices, bio-sensors, MEMS, and systems 4.2 Nanoscale and Post-CMOS Systems - New device structures and process technologies - New memory technologies (flash, phase change memory, STT-RAM, memristor, etc.) - Nanotechnologies, nanowires, nanotubes, graphene, etc. - Quantum computing - Optical devices, computing, and communication